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1. general description the 74lvc00a provides four 2-input nand gates. schmitt trigger action at all inputs makes the ci rcuit tolerant of slower input rise and fall times. inputs can be driven from either 3.3 v or 5 v devices. this feature a llows the use of these devices as translators in mi xed 3.3 v and 5 v applications. 2. features and benefits ? 5 v tolerant inputs for interfacing with 5 v logic ? wide supply voltage range from 1.2 v to 3.6 v ? cmos low-power consumption ? direct interface with ttl levels ? complies with jedec standard: ? jesd8-7a (1.65 v to 1.95 v) ? jesd8-5a (2.3 v to 2.7 v) ? jesd8-c/jesd36 (2.7 v to 3.6 v) ? esd protection: ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-b exceeds 200 v ? cdm jesd22-c101e exceeds 1000 v ? specified from ? 40 c to +85 c and ? 40 c to +125 c 3. ordering information 74lvc00a quad 2-input nand gate rev. 7 ? 25 april 2012 product data sheet table 1. ordering information type number package temperature range name description version 74lvc00ad ? 40 cto+125 c so14 plastic small outl ine package; 14 leads; body width 3.9 mm sot108-1 74lvc00adb ? 40 cto+125 c ssop14 plastic shrink small outline package; 14 leads; body width 5.3 mm sot337-1 74lvc00apw ? 40 cto+125 c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74LVC00ABQ ? 40 cto+125 c dhvqfn14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm sot762-1
74lvc00a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 7 ? 25 april 2012 2 of 14 nxp semiconductors 74lvc00a quad 2-input nand gate 4. functional diagram 5. pinning information 5.1 pinning 5.2 pin description fig 1. logic symbol fig 2. iec logic symbol fig 3. logic diagram for one gate mna212 1a 1y 1b 1 2 3 2a 2y 2b 4 5 6 3a 3y 3b 9 10 8 4a 4y 4b 12 13 11 mna246 3 1 2 & 6 4 5 & 8 9 10 & 11 12 13 & mna211 a b y (1) this is not a supply pin. the substrate is attached to this pad using conductive die atta ch material. there is no electrical or mechanical requi rement to solder this pad. however, if it is soldered, the solder land should remain floating or be connected to gnd. fig 4. pin configuration so14 and (t)ssop14 fig 5. pin configuration dhvqfn14 00 1a v cc 1b 4b 1y 4a 2a 4y 2b 3b 2y 3a gnd 3y 001aac938 1 2 3 4 5 6 7 8 10 9 12 11 14 13 001aac939 00 transparent top view 2y 3a 2b 3b 2a 4y 1y 4a 1b 4b gnd (1) gnd 3y 1a v cc 6 9 5 10 4 11 3 12 2 13 7 8 1 14 terminal 1 index area table 2. pin description symbol pin description 1a to 4a 1, 4, 9, 12 data input 1b to 4b 2, 5, 10, 13 data input 1y to 4y 3, 6, 8,11 data output gnd 7 ground (0 v) v cc 14 supply voltage
74lvc00a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 7 ? 25 april 2012 3 of 14 nxp semiconductors 74lvc00a quad 2-input nand gate 6. functional description [1] h = high voltage level; l = low voltage level; x = don?t care 7. limiting values [1] the minimum input voltage ratings may be excee ded if the input current ratings are observed. [2] the output voltage ratings may be exceeded if the output current ratings are observed. [3] for so14 packages: above 70 c derate linearly with 8 mw/k. for (t)ssop14 packages: above 60 c derate linearly with 5.5 mw/k. for dhvqfn14 packages: above 60 c derate linearly with 4.5 mw/k. 8. recommended operating conditions table 3. function selection [1] input output na nb ny lxh xl h hhl table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +6.5 v i ik input clamping current v i < 0 v ? 50 - ma v i input voltage [1] ? 0.5 +6.5 v i ok output clamping current v o > v cc or v o < 0 v - 50 ma v o output voltage output in high or low-state [2] ? 0.5 v cc + 0.5 v i o output current v o = 0 v to v cc - 50 ma i cc supply current - 100 ma i gnd ground current ? 100 - ma p tot total power dissipation t amb = ? 40 c to +125 c [3] - 500 mw t stg storage temperature ? 65 +150 c table 5. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage 1.65 - 3.6 v functional 1.2 - - v v i input voltage 0 - 5.5 v v o output voltage output high or low state 0 - v cc v t amb ambient temperature ? 40 - +125 c t/ v input transition rise and fall rate v cc = 1.65 v to 2.7 v 0 - 20 ns/v v cc = 2.7 v to 3.6 v 0 - 10 ns/v
74lvc00a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 7 ? 25 april 2012 4 of 14 nxp semiconductors 74lvc00a quad 2-input nand gate 9. static characteristics [1] all typical values are measured at v cc = 3.3 v (unless stated otherwise) and t amb =25 c. table 6. static characteristics at recommended operating conditions. volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 c to +85 c ? 40 c to +125 c unit min typ [1] max min max v ih high-level input voltage v cc = 1.2 v 1.08 - - 1.08 - v v cc = 1.65 v to 1.95 v 0.65 v cc - - 0.65 v cc -v v cc = 2.3 v to 2.7 v 1.7 - - 1.7 - v v cc = 2.7 v to 3.6 v 2.0 - - 2.0 - v v il low-level input voltage v cc = 1.2 v - - 0.12 - 0.12 v v cc = 1.65 v to 1.95 v - - 0.35 v cc -0 . 3 5 v cc v v cc = 2.3 v to 2.7 v - - 0.7 - 0.7 v v cc = 2.7 v to 3.6 v - - 0.8 - 0.8 v v oh high-level output voltage v i =v ih or v il i o = ? 100 a; v cc =1.65vto3.6v v cc ? 0.2 - - v cc ? 0.3 - v i o = ? 4ma; v cc = 1.65 v 1.2 - - 1.05 - v i o = ? 8ma; v cc = 2.3 v 1.8 - - 1.65 - v i o = ? 12 ma; v cc = 2.7 v 2.2 - - 2.05 - v i o = ? 18 ma; v cc = 3.0 v 2.4 - - 2.25 - v i o = ? 24 ma; v cc = 3.0 v 2.2 - - 2.0 - v v ol low-level output voltage v i =v ih or v il i o = 100 a; v cc = 1.65 v to 3.6 v - - 0.2 - 0.3 v i o =4ma; v cc = 1.65 v - - 0.45 - 0.65 v i o =8ma; v cc = 2.3 v - - 0.6 - 0.8 v i o =12ma; v cc = 2.7 v - - 0.4 - 0.6 v i o =24ma; v cc = 3.0 v - - 0.55 - 0.8 v i i input leakage current v cc = 3.6 v; v i =5.5vorgnd - 0.1 5- 20 a i cc supply current v cc = 3.6 v; v i =v cc or gnd; i o =0a -0.110-40 a i cc additional supply current per input pin; v cc = 2.7 v to 3.6 v; v i =v cc ? 0.6 v; i o =0a - 5 500 - 5000 a c i input capacitance v cc = 0 v to 3.6 v; v i =gndtov cc -4 . 0---p f
74lvc00a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 7 ? 25 april 2012 5 of 14 nxp semiconductors 74lvc00a quad 2-input nand gate 10. dynamic characteristics [1] typical values are measured at t amb =25 c and v cc = 1.2 v, 1.8 v, 2.5 v, 2.7 v, and 3.3 v respectively. [2] t pd is the same as t plh and t phl . [3] skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design. [4] c pd is used to determine the dynamic power dissipation (p d in w). p d =c pd v cc 2 f i n+ (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz c l = output load capacitance in pf v cc = supply voltage in volts n = number of inputs switching (c l v cc 2 f o ) = sum of the outputs 11. waveforms table 7. dynamic characteristics voltages are referenced to gnd (ground = 0 v). for test circuit see figure 7 . symbol parameter conditions ? 40 c to +85 c ? 40 c to +125 c unit min typ [1] max min max t pd propagation delay na, nb to ny; see figure 6 [2] v cc =1.2v - 12 - - - ns v cc = 1.65 v to 1.95 v 0.3 3.8 8.4 0.3 9.7 ns v cc = 2.3 v to 2.7 v 1.0 2.2 4.8 1.0 5.7 ns v cc = 2.7 v 1.0 2.3 5.1 1.0 5.9 ns v cc = 3.0 v to 3.6 v 0.5 2.0 4.3 0.5 5.1 ns t sk(o) output skew time v cc = 3.0 v to 3.6 v [3] - - 1.0 - 1.5 ns c pd power dissipation capacitance per gate; v i =gndtov cc [4] v cc = 1.65 v to 1.95 v - 5.6 - - - pf v cc = 2.3 v to 2.7 v - 8.9 - - - pf v cc = 3.0 v to 3.6 v - 11.8 - - - pf v m = 1.5 v at v cc 2.7 v. v m =0.5 v cc at v cc <2.7v. v ol and v oh are typical output voltage levels that occur with the output load. fig 6. the input (na, nb) to output (ny) propagation delays mna213 na, nb input ny output t phl t plh v m v m v ol v oh gnd v i
74lvc00a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 7 ? 25 april 2012 6 of 14 nxp semiconductors 74lvc00a quad 2-input nand gate test data is given in table 8 . definitions for test circuit: r l = load resistance c l = load capacitance including jig and probe capacitance r t = termination resistance should be equal to output impedance z o of the pulse generator fig 7. load circuitry for measuring switching times v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f 001aaf615 v cc v i v o dut c l r t r l pulse generator table 8. test data supply voltage input load v i t r , t f c l r l 1.2 v v cc 2 ns 30 pf 1 k 1.65 v to 1.95 v v cc 2 ns 30 pf 1 k 2.3 v to 2.7 v v cc 2 ns 30 pf 500 2.7v 2.7v 2.5 ns 50 pf 500 3.0vto3.6v 2.7v 2.5 ns 50 pf 500
74lvc00a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 7 ? 25 april 2012 7 of 14 nxp semiconductors 74lvc00a quad 2-input nand gate 12. package outline fig 8. package outline sot108-1 (so14) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot108-1 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 7 8 1 14 y 076e06 ms-012 pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 99-12-27 03-02-19 0 2.5 5 mm scale so14: plastic small outline package; 14 leads; body width 3.9 mm sot108-1
74lvc00a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 7 ? 25 april 2012 8 of 14 nxp semiconductors 74lvc00a quad 2-input nand gate fig 9. package outline sot337-1 (ssop14) unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.25 0.2 7.9 7.6 1.03 0.63 0.9 0.7 1.4 0.9 8 0 o o 0.13 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot337-1 99-12-27 03-02-19 (1) w m b p d h e e z e c v m a x a y 1 7 14 8 a a 1 a 2 l p q detail x l (a ) 3 mo-150 pin 1 index 0 2.5 5 mm scale ssop14: plastic shrink small outline package; 14 leads; body width 5.3 mm sot337-1 a max. 2
74lvc00a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 7 ? 25 april 2012 9 of 14 nxp semiconductors 74lvc00a quad 2-input nand gate fig 10. package outline sot402-1 (tssop14) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index
74lvc00a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 7 ? 25 april 2012 10 of 14 nxp semiconductors 74lvc00a quad 2-input nand gate fig 11. package outline sot762-1 (dhvqfn14) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.1 2.9 d h 1.65 1.35 y 1 2.6 2.4 1.15 0.85 e 1 2 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot762-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot762-1 dhvqfn14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 26 13 9 8 7 1 14 x d e c b a 02-10-17 03-01-27 terminal 1 index area ac c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
74lvc00a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 7 ? 25 april 2012 11 of 14 nxp semiconductors 74lvc00a quad 2-input nand gate 13. abbreviations 14. revision history table 9. abbreviations acronym description cdm charged device model dut device under test esd electrostatic discharge hbm human body model mm machine model ttl transistor-transistor logic table 10. revision history document id release date data sheet status change notice supersedes 74lvc00a v.7 20120425 product data sheet - 74lvc00a v.6 modifications: ? ta b l e 2 : errata in pin description corrected. 74lvc00a v.6 20120106 product data sheet - 74lvc00a v.5 modifications: ? the format of this data sheet has been redesigne d to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? ta b l e 4 , table 5 , table 6 , ta b l e 7 and ta b l e 8 : values added for lower voltage ranges. 74lvc00a v.5 20030904 product specification - 74lvc00a v.4 74lvc00a v.4 20030507 product specification - 74lvc00a v.3 74lvc00a v.3 20020305 product specification - 74lvc00a v.2 74lvc00a v.2 19980428 product specification - 74lvc00a v.1 74lvc00a v.1 19970811 product specification - -
74lvc00a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 7 ? 25 april 2012 12 of 14 nxp semiconductors 74lvc00a quad 2-input nand gate 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74lvc00a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 7 ? 25 april 2012 13 of 14 nxp semiconductors 74lvc00a quad 2-input nand gate export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74lvc00a quad 2-input nand gate ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 25 april 2012 document identifier: 74lvc00a please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 2 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 functional description . . . . . . . . . . . . . . . . . . . 3 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 recommended operating conditions. . . . . . . . 3 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 4 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 5 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 12 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 16 contact information. . . . . . . . . . . . . . . . . . . . . 13 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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